With rapid development of consumer electronics, as an important part of electronics, a power management integrated circuit (PMIC) has advantages such as high integration, high conversion efficiency, and low costs. In recent years, electronics such as smartphones and tablet computers are upgraded rapidly, and a requirement on the power management integrated circuit is increasingly higher.
As shown in FIG. 1, an existing power management integrated circuit includes a gate controller 11, a PMOS power transistor 12, and an NMOS power transistor 13. A gate of the PMOS power transistor 12 and a gate of the NMOS power transistor 13 are both connected to the gate controller 11; a source of the PMOS power transistor 12 is connected to a first reference voltage V1; a drain of the PMOS power transistor 12 is connected to a drain of the NMOS power transistor 13; a source of the NMOS power transistor 13 is grounded; a parasitic inductor L1 is formed between the source of the PMOS power transistor 12 and the first reference voltage, and a parasitic inductor L2 is formed between the source of the NMOS power transistor 13 and the ground.
When the PMOS power transistor 12 is switched off, a current flowing through the PMOS power transistor 12 abruptly changes to 0, while a current of the parasitic inductor L1 cannot change abruptly, and continues flowing through a drain-source capacitor of the PMOS power transistor 12. A high voltage is generated at the source of the PMOS power transistor 12, and the drain of PMOS power transistor 12 is under the high voltage, which directly burns out an internal component of the power management integrated circuit.
To avoid the foregoing situation, in the prior art, some particular MASKs (dopants) are added in a process of manufacturing a chip, to improve withstand voltages of the PMOS power transistor 12 and the NMOS power transistor 13. Because dopants need to be added, manufacturing costs are increased.